1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device, in which a trench with a fine line width is easily formed.
2. Description of Related Art
Generally, Local Oxidation Of Silicon (“LOCOS”) using a nitride layer is used as an isolation technique in the formation of semiconductor devices. In order to complete the LOCOS process, new isolation technologies have been developed including Poly Buffer LOCOS, and Recessed LOCOS (“R-LOCOS”). These technologies have numerous drawbacks. These processes are complicated. Furthermore, these processes do not eliminate the bird's beak phenomenon, which makes inroads into the active region of the silicon oxide layer, which limits high-integration of the semiconductor device. Additionally, these processes create a step between the surface of an active region of the silicon substrate and the surface of the oxide layer of the field region. As such, a planarizing process needs to be performed to reduce the step between these two surfaces.
A Shallow Trench Isolation (“STI”) process was developed. The STI process has several advantages over conventional isolation technology. It has improved isolation properties. It is also very suitable in high-integration of semiconductor devices because of the small spatial requirements.
The STI process includes forming a trench on a field region of a semiconductor substrate. The trench is filled with an oxide layer using a Gap Filling process. A chemical Mechanical Polishing (“CMP”) operation is performed on the oxide layer to planarize the semiconductor substrate and the oxide layer in the trench. As a result, a field oxide layer is formed on the field region of the semiconductor substrate.
The oxide layer, which fills the trench generally includes an O-Tetra-Ethyl-Ortho—Silicate (TEOS) Atmospheric Pressure Chemical Vapor Deposition (APCVD) oxide layer and a High Density Plasma Chemical Vapor Deposition (HDP CVD) oxide layer. These materials have excellent properties for gap-filling and planarizing.
The conventional STI process is illustrated in FIGS. 1 to 4. An oxide layer 11, which functions as a sacrificial layer, is formed on the entire surface of one side of a semiconductor substrate 10. The substrate 10 is a silicon substrate. A nitride layer 13, which functions as a hard mask layer, is deposited on the oxide layer 11. Using photolithography, an opening 14 is formed in a portion of the oxide layer 11 and the nitride layer 13 corresponding to the field region of the semiconductor substrate 10. Using the nitride layer 13 as an etching mask layer, the semiconductor substrate 10 is then etched to form a trench 15 in the field region of the semiconductor substrate 10, as shown in FIG. 1.
Using a thermal oxidation process, an oxide layer 17 is grown on the etched face of the exposed semiconductor substrate 10 in the trench 15. An insulating layer (for example, an oxide layer 19) is deposited in the trench 15. The insulating layer 15 is deposited to a thickness to cover the nitride layer 13 and the trench 15 so that the oxide layer 17 is covered, as shown in FIG. 2.
The oxide layer 19 is planarized on the nitride layer 13 using a CMP process, so that the oxide layer 19 is left only in the trench 15, as shown in FIG. 3. The oxide layer 19 is then densified by a high temperature annealing process. The oxide layer 19 is wet-etched to a certain depth with an HF solution to reduce the height of the oxide layer 19, as shown in FIG. 4. The nitride layer 13 is then etched with a phosphoric acid solution to expose the oxide layer 11. Then, the oxide layer 11 is etched with an HF solution to expose an active region of the semiconductor substrate 10, which completes the STI process.
This prior art STI process, however, has drawbacks. In particular, divot 21 are frequently generated at an upper edge portion of the trench 15, as shown in FIG. 4. The divot 21 forms when the oxide layer 19 is etched using the nitride layer 13 as an etching mask layer so as to reduce the height of the oxide layer 19 because a boundary portion between the oxide layer 19 and the nitride layer 13 is etched faster than the other portion.
A gate oxide layer (e.g., a MOS transistor) is grown on an active region of the semiconductor substrate 10 by a thermal oxidation process. When a divot 21 is present, the gate oxide layer grown on the divot 21 is thinner than that grown on the active region of the semiconductor substrate 10. As a result, the MOS transistor may frequently malfunction whereby the MOS transistor is operated under a threshold voltage VT of the MOS transistor. The electrical properties of the semiconductor device are degraded. There is an increase in current leakage. The yield rate of semiconductor device of suitable quality is reduced. It is possible to reduce the presence of divots 21, but it is very difficult to secure sufficient margins of a wet etching to reduce a generation of the divot 21. The process is difficult, which reduces productivity.
Semiconductor devices with higher degrees of integration may also require finer trench widths. The current photolithography process used with the STI process, however, has limits which prevents the formation of finer trenches.